USR-ES1 embeds Wiznet's W5500 chip, which uses hardware logic gates to implement the transport layer and network layer of the TCP/IP protocol stack (such as TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE, etc.), and integrates The data link layer, physical layer, and 32K bytes of on-chip RAM serve as data transceiving buffers. The host computer main control chip only needs to undertake the processing task of the TCP/IP application layer control information. Thereby, the workload of the host computer for data copying, protocol processing and interrupt processing is greatly saved, and the system utilization and reliability are improved.
During operation, the user can approximate the W5500 as a peripheral RAM of the MCU, which is very simple. The W5500 external interface is a general-purpose 80MHz high-speed SPI, which is used to expand the high-speed Ethernet solution for different platforms. The auto-negotiating LED status shows that the SPI interface is fast and stable. Dimensions and pin compatible Wiznet official module WIZ820io.
80MHz high speed SPI interface
Built-in hardware TCPIP protocol stack, users almost no need to master complex network protocol knowledge
Support for up to 8 Socket connections
Support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE protocol
Integrated data link layer, physical layer
Support power-down wake up
Support high-speed serial peripheral interface (SPI mode 0~3)